<?xml 
version="1.0" encoding="utf-8"?><?xml-stylesheet title="XSL formatting" type="text/xsl" href="https://www.alse.fr/spip.php?page=backend.xslt" ?>
<rss version="2.0" 
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:atom="http://www.w3.org/2005/Atom"
>

<channel xml:lang="fr">
	<title>Formations ALSE (France)</title>
	<link>https://www.alse.fr/</link>
	<description>Leader en France des Formations FPGA &amp; HDL.</description>
	<language>fr</language>
	<generator>SPIP - www.spip.net</generator>
	<atom:link href="https://www.alse.fr/spip.php?id_rubrique=4&amp;page=backend" rel="self" type="application/rss+xml" />

	<image>
		<title>Formations ALSE (France)</title>
		<url>https://www.alse.fr/sites/alse.fr/local/cache-vignettes/L144xH42/siteon0-f94c5.png?1782754102</url>
		<link>https://www.alse.fr/</link>
		<height>42</height>
		<width>144</width>
	</image>



<item xml:lang="fr">
		<title>Bonne Ann&#233;e !</title>
		<link>https://www.alse.fr/Bonne-Annee.html</link>
		<guid isPermaLink="true">https://www.alse.fr/Bonne-Annee.html</guid>
		<dc:date>2025-01-08T08:36:38Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>fr</dc:language>
		
		



		<description>
&lt;p&gt;https://alse-fr.com Toute l'&#233;quipe A.L.S.E vous pr&#233;sente ses Meilleurs Voeux&#8230; &#8230;en attendant de vous accompagner dans vos Projets FPGA et Syst&#232;mes embarqu&#233;s ! Notez notre nouvelle adresse ! ALSE 38b avenue Ren&#233; Coty 75014 PARIS +33 (0)1 84 16 32 32 - FPGA.fr - ALSE.fr&lt;/p&gt;


-
&lt;a href="https://www.alse.fr/-NewsLetter-.html" rel="directory"&gt;NewsLetter&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_texte'&gt;&lt;div class='spip_document_151 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt;
&lt;a href=&#034;https://alse-fr.com&#034; class=&#034;spip_out spip_doc_lien&#034;&gt; &lt;img src='https://www.alse.fr/sites/alse.fr/local/cache-vignettes/L500xH348/hny2026balse800-b0159.jpg?1782754102' width='500' height='348' alt=' ' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;Toute l'&#233;quipe A.L.S.E vous pr&#233;sente ses Meilleurs Voeux&#8230;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&#8230;en attendant de vous accompagner dans vos &lt;a href=&#034;https://www.alse-fr.com&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;Projets FPGA et Syst&#232;mes embarqu&#233;s&lt;/a&gt; !&lt;/p&gt;
&lt;p&gt;Notez notre &lt;strong&gt;nouvelle adresse&lt;/strong&gt; !&lt;/p&gt;
&lt;p&gt;ALSE 38b avenue Ren&#233; Coty 75014 PARIS&lt;br class='manualbr' /&gt;+33 (0)1 84 16 32 32 - &lt;abbr title=&#034;Field Programmable Gate Array. Composants &#233;lectroniques standard que l'utilisateur &#171; personnalise &#187; en utilisant des langages HDL pour impl&#233;menter des fonctions logiques sp&#233;cifiques de son choix. Un fichier de programmation permet (souvent &#224; la mise sous tension) au composant de se configurer et d'avoir le fonctionnement voulu par le concepteur.&#034;&gt;FPGA&lt;/abbr&gt;.fr - ALSE.fr&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="fr">
		<title>Numeric_std issue.</title>
		<link>https://www.alse.fr/Numeric_std-issue.html</link>
		<guid isPermaLink="true">https://www.alse.fr/Numeric_std-issue.html</guid>
		<dc:date>2017-02-21T18:42:37Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>fr</dc:language>
		
		



		<description>
&lt;p&gt;This article describes an error that I found only recently in NUMERIC_STD. Conclusion : do not multiply signed or unsigned vectors by an integer ! Description The IEEE numeric_std library issued (eg) in Nov 1994, and which (as of March 2017) is still used in the latest versions of the Simulation and Synthesis tools, implements incorrectly the multiplications of signed/unsigned vectors by an integer. Fixing these functions is not difficult but my attempt to have the VHDL working (&#8230;)&lt;/p&gt;


-
&lt;a href="https://www.alse.fr/-NewsLetter-.html" rel="directory"&gt;NewsLetter&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This article describes an error that I found only recently in NUMERIC_STD.&lt;/p&gt;
&lt;p&gt;Conclusion : do not multiply signed or unsigned vectors by an integer !&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;Description&lt;/h2&gt;
&lt;p&gt;The IEEE numeric_std library issued (eg) in Nov 1994, and which (as of March 2017) is still used in the latest versions of the Simulation and Synthesis tools, implements incorrectly the multiplications of signed/unsigned vectors by an integer.&lt;/p&gt;
&lt;p&gt;Fixing these functions is not difficult but my attempt to have the &lt;abbr title=&#034;VHDL = VHSIC Hardware Description Language. Ce Langage de Description Mat&#233;rielle (normalis&#233; IEEE 1076) issu du programme du d&#233;partement am&#233;ricain de la d&#233;fense &#171; VHSIC &#187; (1980), &#233;tait destin&#233; au d&#233;part &#224; d&#233;crire sans ambigu&#239;t&#233; le comportement de ces circuits rapides. Aujourd'hui, il c&#232;de graduellement le pas au SystemVerilog mais il reste encore aujourd'hui utilis&#233; (surtout dans la conception FPGA).&#034;&gt;VHDL&lt;/abbr&gt; working group adopt the fix has been so far unsuccessful. But even if I had quickly succeeded, the change would not have been available probably for many (many) years !&lt;/p&gt;
&lt;p&gt;So it's best that you understand the problem and learn how to avoid it.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Functions affected&lt;/h2&gt;
&lt;p&gt;Here are the original prototypes (in IEEE.numeric_std) :&lt;/p&gt;
&lt;div class=&#034;precode&#034;&gt;&lt;pre class='spip_code spip_code_block' dir='ltr' style='text-align:left;'&gt;&lt;code&gt; -- Id: A.17 function &#034;*&#034; ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED((L'length+L'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, L, with a non-negative -- INTEGER, R. R is converted to an UNSIGNED vector of -- SIZE L'length before multiplication. -- Id: A.18 function &#034;*&#034; ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((R'length+R'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, R, with a non-negative -- INTEGER, L. L is converted to an UNSIGNED vector of -- SIZE R'length before multiplication. -- Id: A.19 function &#034;*&#034; ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED((L'length+L'length-1) downto 0) -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is -- converted to a SIGNED vector of SIZE L'length before -- multiplication. -- Id: A.20 function &#034;*&#034; ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED((R'length+R'length-1) downto 0) -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is -- converted to a SIGNED vector of SIZE R'length before -- multiplication.&lt;/code&gt;&lt;/pre&gt;&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Issue&lt;/h2&gt;
&lt;p&gt;As we can see above (in the comments), when multiplying a vector by an integer, the integer is converted into a vector &lt;em class=&#034;spip&#034;&gt;of the same width as the other operand&lt;/em&gt; !!!&lt;/p&gt;
&lt;p&gt;As a consequence, the result's width is forced to two times the width of the signed/unsigned vector, just as if the vector was squared (multiplied by itself), which absolutely does NOT make sense.&lt;/p&gt;
&lt;p&gt;The result is either too short or too large.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Consequences&lt;/h2&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Multiplying a vector by 1 (or a small integer) creates a vector twice as large. &lt;br class='manualbr' /&gt;Quite inefficient, a bit ridiculous, but relatively harmless.&lt;/li&gt;&lt;li&gt; Multiplying a 128-bits vector by 7 (eg) creates a 256-bits results.&lt;br class='manualbr' /&gt;Same remark as above.&lt;/li&gt;&lt;li&gt; The result of Multiplying an 8-bits unsigned vector by 256 is a 16-bits vector (okay by chance) but &lt;strong class=&#034;caractencadre-spip spip&#034;&gt;with a value of ZERO&lt;/strong&gt; ! See the test case included.&lt;br class='manualbr' /&gt;This is definitely VERY WRONG :-( and the multiplication result is not usable.&lt;/li&gt;&lt;li&gt; Multiplying a 8-bits signed vector by 1000 (decimal) produces an incorrect result (actually V * 232) and the result is limited to 16 bits anyway.&lt;br class='manualbr' /&gt;This is also very wrong.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Note that simulators will typically issue truncation warnings &lt;em class=&#034;spip&#034;&gt;during the simulation&lt;/em&gt; (run-time) in the most offending cases, or refuse to compile if the result width is not what the user believed (which is how I uncovered the issue).&lt;br class='manualbr' /&gt;But Synthesis tools will compile and generate hardware which can potentially produce incorrect results, and this is not acceptable.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Are these functions useful ?&lt;/h2&gt;
&lt;p&gt;Certainly. They are required by the principle of numeric_std which is to extend arithmetic operators to vectors that represent numbers (signed and unsigned).&lt;/p&gt;
&lt;p&gt;Moreover, Synthesis tools are usually relatively smart when they see multiplications by constants, in which case they know how to replace the multiplication by adder(s).&lt;/p&gt;
&lt;p&gt;However, their use has been limited (which explains why the incorrect implementation hasn't been reported heavily before).
One can note that the older Synopsys library &#171; std_logic_arith &#187; did not provide the multiplication of signed/unsigned vector by integers, and therefore could not have the same problem.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Repairing NUMERIC_STD ?&lt;/h2&gt;
&lt;p&gt;Fixing the affected functions is not complicated : it suffices to convert the natural or integer into a &lt;strong class=&#034;caractencadre-spip spip&#034;&gt;32-bits&lt;/strong&gt; vector !
The resulting width at least starts making some sense (=Operand width + 32) and no truncation / incorrect result can occur.
If the result is still too large for you (like when you multiply by an integer &lt;em class=&#034;spip&#034;&gt;range&lt;/em&gt;), you just have to resize the result. If you loose information in the resize (you resized into a too short vector), you might think you would get a run time warning&#8230; Unfortunately, this is yet another issue with numeric_std ! The synthesis or a good linter would warn you though.&lt;/p&gt;
&lt;p&gt;&lt;strong class=&#034;caractencadre-spip spip&#034;&gt;BUT, the issue is that numeric_std will probably never be fixed !&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;So you have to take care of your code and make sure you are not affected by the library errors, as explained below.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Conclusion&lt;/h2&gt;
&lt;p&gt;In spite of the library clumsiness (shift operators, and this bug in particular), I still keep recommending using numeric_std instead of other non-IEEE libraries.&lt;/p&gt;
&lt;p&gt;My &lt;strong&gt;VHDL Coding Style Guide&lt;/strong&gt; is updated :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Do not multiply signed/unsigned vectors by Integers.
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Use slices and adders if you multiply by an integer constant&lt;/li&gt;&lt;li&gt; Convert the integer in a properly sized signed or unsigned vector before multiplying.&lt;/li&gt;&lt;li&gt; Do not count on &lt;em class=&#034;spip&#034;&gt;resize&lt;/em&gt; to warn you if the result is incorrect.&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;and the older recommendation remains :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Avoid using shift/rotate operators from numeric_std (use slices &amp; concatenation)&lt;/li&gt;&lt;/ul&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="https://www.alse.fr/sites/alse.fr/IMG/zip/num_std_bug.zip" length="1263" type="application/zip" />
		

	</item>



</channel>

</rss>