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X-WR-CALNAME;VALUE=TEXT:Formations ALSE (France) -- Agenda
X-WR-RELCALID:https://www.alse.fr


BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement308 @ https://www.alse.fr
DTSTAMP:20260417T061820Z
DTSTART;VALUE=DATE:20260921
DTEND;VALUE=DATE:20260926
CREATED:20260417T061820Z
LAST-MODIFIED:20260521T091657Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation VHDL complète (5 jours) avec instructeur à distance.
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=308
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement312 @ https://www.alse.fr
DTSTAMP:20260417T072609Z
DTSTART;VALUE=DATE:20260629
DTEND;VALUE=DATE:20260704
CREATED:20260417T072609Z
LAST-MODIFIED:20260417T092609Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Expert VHDL de 5 jours avec instructeur à distance
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=312
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Altera Quartus & FPGA Timings
UID:evenement311 @ https://www.alse.fr
DTSTAMP:20260417T063708Z
DTSTART;VALUE=DATE:20260622
DTEND;VALUE=DATE:20260626
CREATED:20260417T063708Z
LAST-MODIFIED:20260417T083708Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Altera Quartus + FPGA Timings de 4 jours avec instructeur à distance
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=311
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement310 @ https://www.alse.fr
DTSTAMP:20260417T063447Z
DTSTART;VALUE=DATE:20260615
DTEND;VALUE=DATE:20260618
CREATED:20260417T063447Z
LAST-MODIFIED:20260417T083447Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Tcl/Tk de 3 jours avec instructeur à distance
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=310
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement309 @ https://www.alse.fr
DTSTAMP:20260417T062012Z
DTSTART;VALUE=DATE:20260608
DTEND;VALUE=DATE:20260612
CREATED:20260417T062012Z
LAST-MODIFIED:20260417T082012Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog + SystemVerilog fr Design & Verification (total de 4 jours)
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=309
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement307 @ https://www.alse.fr
DTSTAMP:20251215T065214Z
DTSTART;VALUE=DATE:20260526
DTEND;VALUE=DATE:20260528
CREATED:20251215T065214Z
LAST-MODIFIED:20251215T075214Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation de base « EDDT » à la Conception des systèmes numériques de 2 jours\, à distance
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=307
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Formation Altera Quartus & FPGA Timings
UID:evenement304 @ https://www.alse.fr
DTSTAMP:20251215T064635Z
DTSTART;VALUE=DATE:20260330
DTEND;VALUE=DATE:20260403
CREATED:20251215T064635Z
LAST-MODIFIED:20260311T164528Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Quartus & Timings de 4 jours à distance
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=304
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement305 @ https://www.alse.fr
DTSTAMP:20251215T064820Z
DTSTART;VALUE=DATE:20260401
DTEND;VALUE=DATE:20260403
CREATED:20251215T064820Z
LAST-MODIFIED:20251215T074820Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation : Les Classes de Vérification SystemVerilog de 2 jours\, à distance.
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=305
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement301 @ https://www.alse.fr
DTSTAMP:20251215T063353Z
DTSTART;VALUE=DATE:20260323
DTEND;VALUE=DATE:20260328
CREATED:20251215T063353Z
LAST-MODIFIED:20260207T205337Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Comprehensive VHDL de 5 jours à distance
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=301
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement303 @ https://www.alse.fr
DTSTAMP:20251215T064434Z
DTSTART;VALUE=DATE:20260316
DTEND;VALUE=DATE:20260320
CREATED:20251215T064434Z
LAST-MODIFIED:20251215T074434Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation SystemVerilog for Design & Verification de 4 jours\, à distance
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=303
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement302 @ https://www.alse.fr
DTSTAMP:20251215T064251Z
DTSTART;VALUE=DATE:20260309
DTEND;VALUE=DATE:20260312
CREATED:20251215T064251Z
LAST-MODIFIED:20251215T074251Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Tcl/Tk de 3 jours à distance
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=302
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement299 @ https://www.alse.fr
DTSTAMP:20250517T024227Z
DTSTART;VALUE=DATE:20251117
DTEND;VALUE=DATE:20251121
CREATED:20250517T024227Z
LAST-MODIFIED:20250904T153546Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation au Verilog et SystemVerilog (1+3 jours) pour Conception & Vérification
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=299
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Python & Scientific Computing
UID:evenement297 @ https://www.alse.fr
DTSTAMP:20250517T023905Z
DTSTART;VALUE=DATE:20251112
DTEND;VALUE=DATE:20251115
CREATED:20250517T023905Z
LAST-MODIFIED:20250517T043905Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Python & Scientific computing de 3 jours
CATEGORIES:Python & Scientific Computing
URL:https://www.alse.fr/Python-Scientific-Computing.html?id_evenement=297
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement298 @ https://www.alse.fr
DTSTAMP:20250517T024103Z
DTSTART;VALUE=DATE:20251103
DTEND;VALUE=DATE:20251108
CREATED:20250517T024103Z
LAST-MODIFIED:20250904T153109Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation au Langage VHDL de 5 jours
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=298
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement300 @ https://www.alse.fr
DTSTAMP:20250517T024356Z
DTSTART;VALUE=DATE:20251106
DTEND;VALUE=DATE:20251108
CREATED:20250517T024356Z
LAST-MODIFIED:20250517T044531Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation aux Classes de Vérification SystemVerilog (2 jours)/ !\ il faut maîtriser le SystemVerilog pour conception et vérification (formation préalable requise)
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=300
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement296 @ https://www.alse.fr
DTSTAMP:20250517T022947Z
DTSTART;VALUE=DATE:20251013
DTEND;VALUE=DATE:20251018
CREATED:20250517T022947Z
LAST-MODIFIED:20250517T042947Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Expert VHDL de 5 jours
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=296
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime & Timings
UID:evenement295 @ https://www.alse.fr
DTSTAMP:20250517T022836Z
DTSTART;VALUE=DATE:20251006
DTEND;VALUE=DATE:20251010
CREATED:20250517T022836Z
LAST-MODIFIED:20250517T042836Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation à la conception des FPGAs Altera avec Quartus et aux Timings (SDC)
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=295
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement294 @ https://www.alse.fr
DTSTAMP:20250517T022608Z
DTSTART;VALUE=DATE:20251002
DTEND;VALUE=DATE:20251004
CREATED:20250517T022608Z
LAST-MODIFIED:20250517T042608Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation à la Conception des Systèmes Numériques (2 jours)
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=294
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement293 @ https://www.alse.fr
DTSTAMP:20250517T022334Z
DTSTART;VALUE=DATE:20250915
DTEND;VALUE=DATE:20250920
CREATED:20250517T022334Z
LAST-MODIFIED:20250517T042403Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation au Langage VHDL de 5 jours
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=293
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement292 @ https://www.alse.fr
DTSTAMP:20250517T022217Z
DTSTART;VALUE=DATE:20250623
DTEND;VALUE=DATE:20250625
CREATED:20250517T022217Z
LAST-MODIFIED:20250517T042505Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation à la Conception des Systèmes Numériques
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=292
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement291 @ https://www.alse.fr
DTSTAMP:20250517T021723Z
DTSTART;VALUE=DATE:20250602
DTEND;VALUE=DATE:20250607
CREATED:20250517T021723Z
LAST-MODIFIED:20250517T041723Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Expert-VHDL de 5 jours
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=291
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement287 @ https://www.alse.fr
DTSTAMP:20241125T105828Z
DTSTART;VALUE=DATE:20250331
DTEND;VALUE=DATE:20250405
CREATED:20241125T105828Z
LAST-MODIFIED:20241125T105828Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Expert-VHDL de 5 jours.
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=287
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement286 @ https://www.alse.fr
DTSTAMP:20241125T105726Z
DTSTART;VALUE=DATE:20250326
DTEND;VALUE=DATE:20250329
CREATED:20241125T105726Z
LAST-MODIFIED:20241125T105726Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Tcl/Tk complète de 3 jours.
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=286
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement288 @ https://www.alse.fr
DTSTAMP:20241125T110010Z
DTSTART;VALUE=DATE:20250327
DTEND;VALUE=DATE:20250329
CREATED:20241125T110010Z
LAST-MODIFIED:20241125T110010Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation (2 jours) sur les Classes SystemVerilog pour la vérification\, en préparation à la formation UVM.
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=288
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement285 @ https://www.alse.fr
DTSTAMP:20241125T105543Z
DTSTART;VALUE=DATE:20250324
DTEND;VALUE=DATE:20250326
CREATED:20241125T105543Z
LAST-MODIFIED:20241125T105543Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation « EDDT » à la Conception des Systèmes Numériques. (2 jours)
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=285
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime & Timings
UID:evenement290 @ https://www.alse.fr
DTSTAMP:20250124T081735Z
DTSTART;VALUE=DATE:20250317
DTEND;VALUE=DATE:20250321
CREATED:20250124T081735Z
LAST-MODIFIED:20250124T091735Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Altera Quartus & Timings de 4 jours
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=290
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement282 @ https://www.alse.fr
DTSTAMP:20241125T105144Z
DTSTART;VALUE=DATE:20250311
DTEND;VALUE=DATE:20250314
CREATED:20241125T105144Z
LAST-MODIFIED:20241125T105144Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation « SystemVerilog for Design & Verification » de 3 jours
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=282
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement283 @ https://www.alse.fr
DTSTAMP:20241125T105326Z
DTSTART;VALUE=DATE:20250310
DTEND;VALUE=DATE:20250311
CREATED:20241125T105326Z
LAST-MODIFIED:20241125T105326Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog intense (1 journée) pour utilisateurs VHDL et en préparation de la formation SystemVerilog.
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=283
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement284 @ https://www.alse.fr
DTSTAMP:20241125T105326Z
DTSTART;VALUE=DATE:20250310
DTEND;VALUE=DATE:20250311
CREATED:20241125T105326Z
LAST-MODIFIED:20241125T105326Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog intense (1 journée) pour utilisateurs VHDL et en préparation de la formation SystemVerilog.
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=284
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement289 @ https://www.alse.fr
DTSTAMP:20250115T193647Z
DTSTART;VALUE=DATE:20250203
DTEND;VALUE=DATE:20250208
CREATED:20250115T193647Z
LAST-MODIFIED:20250115T193647Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Comprehensive VHDL de 5 jours.
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=289
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement281 @ https://www.alse.fr
DTSTAMP:20241024T053302Z
DTSTART;VALUE=DATE:20241216
DTEND;VALUE=DATE:20241221
CREATED:20241024T053302Z
LAST-MODIFIED:20241024T053302Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation complète au Langage VHDL de 5 jours.
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=281
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement272 @ https://www.alse.fr
DTSTAMP:20240620T072743Z
DTSTART;VALUE=DATE:20241209
DTEND;VALUE=DATE:20241214
CREATED:20240620T072743Z
LAST-MODIFIED:20240620T072743Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Expert-VHDL (avec instructeur à distance)
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=272
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement280 @ https://www.alse.fr
DTSTAMP:20241009T130244Z
DTSTART;VALUE=DATE:20241202
DTEND;VALUE=DATE:20241204
CREATED:20241009T130244Z
LAST-MODIFIED:20241009T130244Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation à la Conception des Systèmes Numériques (FPGA/ASIC)
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=280
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement277 @ https://www.alse.fr
DTSTAMP:20240621T123709Z
DTSTART;VALUE=DATE:20241126
DTEND;VALUE=DATE:20241129
CREATED:20240621T123709Z
LAST-MODIFIED:20240912T083027Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation SystemVerilog for Design & Verification de 4 jours
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=277
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement278 @ https://www.alse.fr
DTSTAMP:20240912T083216Z
DTSTART;VALUE=DATE:20241125
DTEND;VALUE=DATE:20241126
CREATED:20240912T083216Z
LAST-MODIFIED:20240912T083216Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog for VHDL Designers (1 journée)
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=278
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL for Assertions-Based Verification
UID:evenement279 @ https://www.alse.fr
DTSTAMP:20241009T125147Z
DTSTART;VALUE=DATE:20241121
DTEND;VALUE=DATE:20241123
CREATED:20241009T125147Z
LAST-MODIFIED:20241009T125147Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation aux Assertions\, à distance\, en 2x 1/2 journées.
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=279
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement275 @ https://www.alse.fr
DTSTAMP:20240621T110236Z
DTSTART;VALUE=DATE:20241112
DTEND;VALUE=DATE:20241115
CREATED:20240621T110236Z
LAST-MODIFIED:20240621T110236Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Tcl/Tk de 3 jours (instructeur à distance)
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=275
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement271 @ https://www.alse.fr
DTSTAMP:20240620T072621Z
DTSTART;VALUE=DATE:20241104
DTEND;VALUE=DATE:20241109
CREATED:20240620T072621Z
LAST-MODIFIED:20241024T053340Z 
LOCATION:A distance (OnLine) - COMPLETE
DESCRIPTION:Formation Comprehensive VHDL (instructeur à distance)
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=271
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Enhanced UVM Adopter
UID:evenement270 @ https://www.alse.fr
DTSTAMP:20240620T072503Z
DTSTART;VALUE=DATE:20241021
DTEND;VALUE=DATE:20241025
CREATED:20240620T072503Z
LAST-MODIFIED:20240620T072503Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation à la Méthodologie UVM (avec instructeur à distance) / !\ Attention aux pré-requis…
CATEGORIES:Enhanced UVM Adopter
URL:https://www.alse.fr/Enhanced-UVM-Adopter-Class.html?id_evenement=270
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement274 @ https://www.alse.fr
DTSTAMP:20240621T101835Z
DTSTART;VALUE=DATE:20241014
DTEND;VALUE=DATE:20241019
CREATED:20240621T101835Z
LAST-MODIFIED:20240621T101835Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Expert-VHDL de 5 jours (instructeur à distance)
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=274
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement269 @ https://www.alse.fr
DTSTAMP:20240620T072337Z
DTSTART;VALUE=DATE:20241010
DTEND;VALUE=DATE:20241012
CREATED:20240620T072337Z
LAST-MODIFIED:20240620T072337Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Essential Digital Design Techniques (instructeur à distance)
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=269
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement268 @ https://www.alse.fr
DTSTAMP:20240620T071116Z
DTSTART;VALUE=DATE:20241007
DTEND;VALUE=DATE:20241009
CREATED:20240620T071116Z
LAST-MODIFIED:20240620T071116Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation aux Classes de Vérification SystemVerilog (préparation à UVM)
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=268
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement273 @ https://www.alse.fr
DTSTAMP:20240621T101404Z
DTSTART;VALUE=DATE:20241001
DTEND;VALUE=DATE:20241005
CREATED:20240621T101404Z
LAST-MODIFIED:20240621T101404Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Quartus & Timings de 4 jours
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=273
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement267 @ https://www.alse.fr
DTSTAMP:20240620T070915Z
DTSTART;VALUE=DATE:20240916
DTEND;VALUE=DATE:20240921
CREATED:20240620T070915Z
LAST-MODIFIED:20240620T070915Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Comprehensive VHDL à distance
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=267
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL for Assertions-Based Verification
UID:evenement276 @ https://www.alse.fr
DTSTAMP:20240621T121349Z
DTSTART;VALUE=DATE:20240912
DTEND;VALUE=DATE:20240914
CREATED:20240621T121349Z
LAST-MODIFIED:20240621T121349Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation aux Assertions PSL - Deux 1/2 journées - Instructeur à distance
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=276
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement266 @ https://www.alse.fr
DTSTAMP:20240426T140415Z
DTSTART;VALUE=DATE:20240701
DTEND;VALUE=DATE:20240705
CREATED:20240426T140415Z
LAST-MODIFIED:20240426T140415Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Quartus & Timings (4 jours)
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=266
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement261 @ https://www.alse.fr
DTSTAMP:20240410T152837Z
DTSTART;VALUE=DATE:20240617
DTEND;VALUE=DATE:20240619
CREATED:20240410T152837Z
LAST-MODIFIED:20240410T152837Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation : « Essential Digital Design Techniques »
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=261
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement263 @ https://www.alse.fr
DTSTAMP:20240426T140011Z
DTSTART;VALUE=DATE:20240603
DTEND;VALUE=DATE:20240608
CREATED:20240426T140011Z
LAST-MODIFIED:20240426T140011Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Expert VHDL (5 jours)
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=263
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement264 @ https://www.alse.fr
DTSTAMP:20240426T140137Z
DTSTART;VALUE=DATE:20240528
DTEND;VALUE=DATE:20240531
CREATED:20240426T140137Z
LAST-MODIFIED:20240426T140137Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation SystemVerilog (3 jours)
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=264
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement265 @ https://www.alse.fr
DTSTAMP:20240426T140226Z
DTSTART;VALUE=DATE:20240527
DTEND;VALUE=DATE:20240528
CREATED:20240426T140226Z
LAST-MODIFIED:20240426T140236Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog Primer (1 jour)
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=265
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement262 @ https://www.alse.fr
DTSTAMP:20240426T135859Z
DTSTART;VALUE=DATE:20240513
DTEND;VALUE=DATE:20240518
CREATED:20240426T135859Z
LAST-MODIFIED:20240426T135859Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation complète VHDL (5 jours)
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=262
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL for Assertions-Based Verification
UID:evenement260 @ https://www.alse.fr
DTSTAMP:20231227T123408Z
DTSTART;VALUE=DATE:20240506
DTEND;VALUE=DATE:20240508
CREATED:20231227T123408Z
LAST-MODIFIED:20231227T123558Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation intensive (2 x 1/2j) aux Assertions PSL.
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=260
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Enhanced UVM Adopter
UID:evenement257 @ https://www.alse.fr
DTSTAMP:20231227T111947Z
DTSTART;VALUE=DATE:20240402
DTEND;VALUE=DATE:20240406
CREATED:20231227T111947Z
LAST-MODIFIED:20231227T111947Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation UVM (4 jours). Attention aux pré-requis !!!
CATEGORIES:Enhanced UVM Adopter
URL:https://www.alse.fr/Enhanced-UVM-Adopter-Class.html?id_evenement=257
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement258 @ https://www.alse.fr
DTSTAMP:20231227T112426Z
DTSTART;VALUE=DATE:20240402
DTEND;VALUE=DATE:20240405
CREATED:20231227T112426Z
LAST-MODIFIED:20231227T112426Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Tcl/Tk de 3 jours.
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=258
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement256 @ https://www.alse.fr
DTSTAMP:20231227T111720Z
DTSTART;VALUE=DATE:20240328
DTEND;VALUE=DATE:20240330
CREATED:20231227T111720Z
LAST-MODIFIED:20231227T111720Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation EDDT (2 jours) aux bases de l'électronique digitale et aux composants programmables FPGA ou ASIC.
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=256
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement254 @ https://www.alse.fr
DTSTAMP:20231227T110819Z
DTSTART;VALUE=DATE:20240325
DTEND;VALUE=DATE:20240329
CREATED:20231227T110819Z
LAST-MODIFIED:20231227T110819Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Conception Intel-FPGA avec Quartus & Timing course de 4 jours
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=254
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement255 @ https://www.alse.fr
DTSTAMP:20231227T111121Z
DTSTART;VALUE=DATE:20240325
DTEND;VALUE=DATE:20240327
CREATED:20231227T111121Z
LAST-MODIFIED:20231227T111121Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Les Classes de Vérification SystemVerilog (2 jours) en préparation à UVM.
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=255
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement253 @ https://www.alse.fr
DTSTAMP:20231227T110435Z
DTSTART;VALUE=DATE:20240318
DTEND;VALUE=DATE:20240323
CREATED:20231227T110435Z
LAST-MODIFIED:20231227T110435Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Expert VHDL de 5 jours.
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=253
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement251 @ https://www.alse.fr
DTSTAMP:20231227T105945Z
DTSTART;VALUE=DATE:20240312
DTEND;VALUE=DATE:20240315
CREATED:20231227T105945Z
LAST-MODIFIED:20231227T105945Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation SystemVerilog for Design & Verification de 3 jours.
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=251
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement252 @ https://www.alse.fr
DTSTAMP:20231227T110232Z
DTSTART:20240311T073000Z
DTEND:20240311T163000Z
CREATED:20231227T110232Z
LAST-MODIFIED:20231228T093918Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Verilog Primer (pour utilisateurs VHDL)\, d'une journée\, indispensable pour préparer la formation SystemVerilog !
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=252
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement249 @ https://www.alse.fr
DTSTAMP:20231227T105512Z
DTSTART;VALUE=DATE:20240205
DTEND;VALUE=DATE:20240210
CREATED:20231227T105512Z
LAST-MODIFIED:20231227T105512Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Comprehensive VHDL de 5 jours
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=249
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Yocto
UID:evenement250 @ https://www.alse.fr
DTSTAMP:20231227T105702Z
DTSTART;VALUE=DATE:20240205
DTEND;VALUE=DATE:20240210
CREATED:20231227T105702Z
LAST-MODIFIED:20231227T105702Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Yocto à distance en Anglais avec instructeur ALSE (Français)
CATEGORIES:Yocto
URL:https://www.alse.fr/Yocto.html?id_evenement=250
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement247 @ https://www.alse.fr
DTSTAMP:20231015T211421Z
DTSTART;VALUE=DATE:20231219
DTEND;VALUE=DATE:20231223
CREATED:20231015T211421Z
LAST-MODIFIED:20231015T211421Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Conception Intel FPGA avec Quartus
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=247
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement246 @ https://www.alse.fr
DTSTAMP:20231015T200836Z
DTSTART;VALUE=DATE:20231211
DTEND;VALUE=DATE:20231213
CREATED:20231015T200836Z
LAST-MODIFIED:20231015T200836Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation aux Classes de Vérification SystemVerilog (en préparation à UVM)
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=246
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement248 @ https://www.alse.fr
DTSTAMP:20231015T211551Z
DTSTART;VALUE=DATE:20231204
DTEND;VALUE=DATE:20231209
CREATED:20231015T211551Z
LAST-MODIFIED:20231015T211551Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Expert-VHDL
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=248
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL for Assertions-Based Verification
UID:evenement259 @ https://www.alse.fr
DTSTAMP:20231227T112810Z
DTSTART;VALUE=DATE:20231206
DTEND;VALUE=DATE:20231208
CREATED:20231227T112810Z
LAST-MODIFIED:20231227T112810Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Assertions PSL de 2 x 1/2 journées
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=259
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement244 @ https://www.alse.fr
DTSTAMP:20230913T143626Z
DTSTART;VALUE=DATE:20231121
DTEND;VALUE=DATE:20231124
CREATED:20230913T143626Z
LAST-MODIFIED:20230913T143626Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation SystemVerilog for Design & Verification. Connaissance préalable du langage Verilog indispensable (ou participation à la journée du 20 Novembre).
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=244
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement245 @ https://www.alse.fr
DTSTAMP:20230913T143729Z
DTSTART;VALUE=DATE:20231120
DTEND;VALUE=DATE:20231121
CREATED:20230913T143729Z
LAST-MODIFIED:20230913T143729Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Verilog Primer préparatoire à la formation SystemVerilog.
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=245
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement243 @ https://www.alse.fr
DTSTAMP:20230904T091120Z
DTSTART;VALUE=DATE:20231113
DTEND;VALUE=DATE:20231118
CREATED:20230904T091120Z
LAST-MODIFIED:20230913T143845Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Comprehensive VHDL (5 jours)
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=243
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL for Assertions-Based Verification
UID:evenement241 @ https://www.alse.fr
DTSTAMP:20230602T175351Z
DTSTART;VALUE=DATE:20231109
DTEND;VALUE=DATE:20231111
CREATED:20230602T175351Z
LAST-MODIFIED:20230602T175351Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation à la Vérification par Assertions PSL (2 demi-journées)
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=241
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Enhanced UVM Adopter
UID:evenement239 @ https://www.alse.fr
DTSTAMP:20230602T174522Z
DTSTART;VALUE=DATE:20231106
DTEND;VALUE=DATE:20231110
CREATED:20230602T174522Z
LAST-MODIFIED:20230602T174522Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation UVM (attention aux pré-requis !)
CATEGORIES:Enhanced UVM Adopter
URL:https://www.alse.fr/Enhanced-UVM-Adopter-Class.html?id_evenement=239
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement240 @ https://www.alse.fr
DTSTAMP:20230602T174920Z
DTSTART;VALUE=DATE:20231106
DTEND;VALUE=DATE:20231109
CREATED:20230602T174920Z
LAST-MODIFIED:20230602T174920Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Tcl/Tk\, le couteau Suisse !
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=240
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement238 @ https://www.alse.fr
DTSTAMP:20230602T174402Z
DTSTART;VALUE=DATE:20231016
DTEND;VALUE=DATE:20231021
CREATED:20230602T174402Z
LAST-MODIFIED:20230602T174402Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Expert VHDL
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=238
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement237 @ https://www.alse.fr
DTSTAMP:20230602T174223Z
DTSTART;VALUE=DATE:20231009
DTEND;VALUE=DATE:20231011
CREATED:20230602T174223Z
LAST-MODIFIED:20230602T174223Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation aux bases de la conception des circuits digitaux.
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=237
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement242 @ https://www.alse.fr
DTSTAMP:20230825T093554Z
DTSTART;VALUE=DATE:20231003
DTEND;VALUE=DATE:20231007
CREATED:20230825T093554Z
LAST-MODIFIED:20230825T093554Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Intel Quartus complète de 4 jours
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=242
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement236 @ https://www.alse.fr
DTSTAMP:20230602T173934Z
DTSTART;VALUE=DATE:20230926
DTEND;VALUE=DATE:20230929
CREATED:20230602T173934Z
LAST-MODIFIED:20230602T174003Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation SystemVerilog for Design & Verification
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=236
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement235 @ https://www.alse.fr
DTSTAMP:20230602T173725Z
DTSTART;VALUE=DATE:20230925
DTEND;VALUE=DATE:20230926
CREATED:20230602T173725Z
LAST-MODIFIED:20230602T173725Z 
LOCATION:à distance (OnLine)
DESCRIPTION:Formation Verilog Primer (préparatoire au SystemVerilog)
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=235
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement234 @ https://www.alse.fr
DTSTAMP:20230602T173559Z
DTSTART;VALUE=DATE:20230918
DTEND;VALUE=DATE:20230923
CREATED:20230602T173559Z
LAST-MODIFIED:20230602T173559Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Comprehensive VHDL à distance
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=234
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement233 @ https://www.alse.fr
DTSTAMP:20230505T130602Z
DTSTART;VALUE=DATE:20230703
DTEND;VALUE=DATE:20230707
CREATED:20230505T130602Z
LAST-MODIFIED:20230505T130602Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Quartus à distance
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=233
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement228 @ https://www.alse.fr
DTSTAMP:20230206T235021Z
DTSTART;VALUE=DATE:20230626
DTEND;VALUE=DATE:20230701
CREATED:20230206T235021Z
LAST-MODIFIED:20230505T130410Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Expert-VHDL (5 jours)
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=228
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement231 @ https://www.alse.fr
DTSTAMP:20230419T080345Z
DTSTART;VALUE=DATE:20230627
DTEND;VALUE=DATE:20230629
CREATED:20230419T080345Z
LAST-MODIFIED:20230505T130852Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation à la Conception des Systèmes Numériques
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=231
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement232 @ https://www.alse.fr
DTSTAMP:20230419T080612Z
DTSTART;VALUE=DATE:20230623
DTEND;VALUE=DATE:20230624
CREATED:20230419T080612Z
LAST-MODIFIED:20230505T130733Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formations (2 jours) aux Classes du SystemVerilog.Notamment en préparation de la formation UVM.
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=232
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement225 @ https://www.alse.fr
DTSTAMP:20230206T234637Z
DTSTART;VALUE=DATE:20230613
DTEND;VALUE=DATE:20230617
CREATED:20230206T234637Z
LAST-MODIFIED:20230419T080037Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation SystemVerilog for Design & Verification (3 jours)
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=225
SEQUENCE:2

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement226 @ https://www.alse.fr
DTSTAMP:20230206T234740Z
DTSTART;VALUE=DATE:20230613
DTEND;VALUE=DATE:20230614
CREATED:20230206T234740Z
LAST-MODIFIED:20230419T080120Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Verilog Primer (1 jour) pour préparer SystemVerilog
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=226
SEQUENCE:2

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement230 @ https://www.alse.fr
DTSTAMP:20230419T071733Z
DTSTART;VALUE=DATE:20230605
DTEND;VALUE=DATE:20230610
CREATED:20230419T071733Z
LAST-MODIFIED:20230419T071733Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation VHDL intégrale
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=230
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement227 @ https://www.alse.fr
DTSTAMP:20230206T234843Z
DTSTART;VALUE=DATE:20230515
DTEND;VALUE=DATE:20230518
CREATED:20230206T234843Z
LAST-MODIFIED:20230206T234843Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Tcl/Tk (3 jours)
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=227
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:PSL
UID:evenement219 @ https://www.alse.fr
DTSTAMP:20230104T203638Z
DTSTART:20230406T063000Z
DTEND:20230407T110000Z
CREATED:20230104T203638Z
LAST-MODIFIED:20230104T203638Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation ABV PSL de 2 x 1/2 journées
CATEGORIES:PSL for Assertions-Based Verification
URL:https://www.alse.fr/Assertion-Based-Verification-with-PSL.html?id_evenement=219
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Python & Scientific Computing
UID:evenement223 @ https://www.alse.fr
DTSTAMP:20230206T234124Z
DTSTART;VALUE=DATE:20230403
DTEND;VALUE=DATE:20230407
CREATED:20230206T234124Z
LAST-MODIFIED:20230206T234124Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Essential Python (4 jours) - à distance (OnLine)
CATEGORIES:Python & Scientific Computing
URL:https://www.alse.fr/Python-Scientific-Computing.html?id_evenement=223
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Digital Design Techniques
UID:evenement218 @ https://www.alse.fr
DTSTAMP:20230104T203342Z
DTSTART;VALUE=DATE:20230403
DTEND;VALUE=DATE:20230405
CREATED:20230104T203342Z
LAST-MODIFIED:20230104T203342Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Conception des Systèmes Numériques « EDDT » de 2 jours
CATEGORIES:Essential Digital Design Techniques
URL:https://www.alse.fr/Essential-Digital-Design-Techniques.html?id_evenement=218
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement224 @ https://www.alse.fr
DTSTAMP:20230206T234352Z
DTSTART;VALUE=DATE:20230320
DTEND;VALUE=DATE:20230325
CREATED:20230206T234352Z
LAST-MODIFIED:20230206T234352Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Comprehensive VHDL (5 jours)
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=224
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement229 @ https://www.alse.fr
DTSTAMP:20230308T234739Z
DTSTART;VALUE=DATE:20230321
DTEND;VALUE=DATE:20230325
CREATED:20230308T234739Z
LAST-MODIFIED:20230308T234739Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation complète Quartus Prime 4 jours
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=229
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement216 @ https://www.alse.fr
DTSTAMP:20230104T203030Z
DTSTART;VALUE=DATE:20230301
DTEND;VALUE=DATE:20230304
CREATED:20230104T203030Z
LAST-MODIFIED:20230206T233538Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation SystemVerilog for Design and Verification (3 jours) - COMPLETE
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=216
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement215 @ https://www.alse.fr
DTSTAMP:20230104T202851Z
DTSTART;VALUE=DATE:20230228
DTEND;VALUE=DATE:20230301
CREATED:20230104T202851Z
LAST-MODIFIED:20230206T233807Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Verilog Primer (1 jour intense) - COMPLETE
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=215
SEQUENCE:2

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:SystemVerilog for Design & Verification
UID:evenement220 @ https://www.alse.fr
DTSTAMP:20230206T233427Z
DTSTART;VALUE=DATE:20230214
DTEND;VALUE=DATE:20230217
CREATED:20230206T233427Z
LAST-MODIFIED:20230206T233427Z
DESCRIPTION:Formation SystemVerilog for Design & Verification - COMPLETE
CATEGORIES:SystemVerilog for Design & Verification
URL:https://www.alse.fr/SystemVerilog-for-Design.html?id_evenement=220
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Verilog Primer (pour utilisateurs VHDL)
UID:evenement221 @ https://www.alse.fr
DTSTAMP:20230206T233720Z
DTSTART;VALUE=DATE:20230213
DTEND;VALUE=DATE:20230214
CREATED:20230206T233720Z
LAST-MODIFIED:20230206T233720Z
DESCRIPTION:Verilog Primer (1 jour) - COMPLETE
CATEGORIES:Verilog Primer (pour utilisateurs VHDL)
URL:https://www.alse.fr/Fast-Track-Verilog-pour-utilisateurs-VHDL.html?id_evenement=221
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Comprehensive VHDL
UID:evenement213 @ https://www.alse.fr
DTSTAMP:20230104T202235Z
DTSTART;VALUE=DATE:20230130
DTEND;VALUE=DATE:20230204
CREATED:20230104T202235Z
LAST-MODIFIED:20230104T202235Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Comprehensive VHDL modulaire de 5 jours
CATEGORIES:Comprehensive VHDL
URL:https://www.alse.fr/Comprehensive-VHDL.html?id_evenement=213
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Classes de Vérification SystemVerilog
UID:evenement214 @ https://www.alse.fr
DTSTAMP:20230104T202730Z
DTSTART;VALUE=DATE:20230202
DTEND;VALUE=DATE:20230204
CREATED:20230104T202730Z
LAST-MODIFIED:20230104T202730Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation de 2 jours aux Classes de Vérification SystemVerilog\, pour préparer la formation UVM.
CATEGORIES:Classes de Vérification SystemVerilog
URL:https://www.alse.fr/Verification-a-l-aide-des-Classes-SystemVerilog.html?id_evenement=214
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Python & Scientific Computing
UID:evenement222 @ https://www.alse.fr
DTSTAMP:20230206T234023Z
DTSTART;VALUE=DATE:20230131
DTEND;VALUE=DATE:20230204
CREATED:20230206T234023Z
LAST-MODIFIED:20230206T234023Z
DESCRIPTION:Formation Essential Python (4 jours)
CATEGORIES:Python & Scientific Computing
URL:https://www.alse.fr/Python-Scientific-Computing.html?id_evenement=222
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Quartus Prime
UID:evenement212 @ https://www.alse.fr
DTSTAMP:20220914T215633Z
DTSTART;VALUE=DATE:20221121
DTEND;VALUE=DATE:20221125
CREATED:20220914T215633Z
LAST-MODIFIED:20220914T215633Z 
LOCATION:A distance (OnLine)
DESCRIPTION:Formation Quartus & Timing
CATEGORIES:Altera Quartus & FPGA Timings
URL:https://www.alse.fr/Conception-Altera-Quartus-II.html?id_evenement=212
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Essential Tcl/Tk
UID:evenement207 @ https://www.alse.fr
DTSTAMP:20220529T193722Z
DTSTART;VALUE=DATE:20221102
DTEND;VALUE=DATE:20221105
CREATED:20220529T193722Z
LAST-MODIFIED:20220531T220706Z 
LOCATION:à distance (OnLIne)
DESCRIPTION:Formation Tcl/Tk (3 jours)
CATEGORIES:Essential Tcl/Tk
URL:https://www.alse.fr/Essential-Tcl-Tk.html?id_evenement=207
SEQUENCE:1

STATUS:CONFIRMED
END:VEVENT
BEGIN:VEVENT
SUMMARY:Expert VHDL
UID:evenement206 @ https://www.alse.fr
DTSTAMP:20220529T193559Z
DTSTART;VALUE=DATE:20221017
DTEND;VALUE=DATE:20221022
CREATED:20220529T193559Z
LAST-MODIFIED:20220529T193559Z 
LOCATION:ALSE Paris 13è ou à distance (OnLine)
DESCRIPTION:Formation Expert VHDL (5 jours)
CATEGORIES:Expert VHDL
URL:https://www.alse.fr/Expert-VHDL.html?id_evenement=206
SEQUENCE:0

STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR