Articles syndiqués tirés de ce site

Aurora on Avant !

Octobre 2025

Discover how you can create an inter-FPGA Aurora link on the latest Lattice FPGA families. In 2025, the Lattice Avant™ 16nm FinFET platform became available. Taking advantage of its know-how in terms of low cost and low power consumption, Lattice now enters the mid-range FPGA market with (…)

ALSE Aurora 8B/10B on Efinix

Août 2025

We have ported our Aurora 8B/10B on Efinix Titanium. We have built a nice and convincing demo based on the Efinix Titanium kit. This demo is described in the document below. In principle, this type of document is confidential and accessible only after signing a mutual NDA. Please understand that (…)

ALSE Aurora 64B/66B on Efinix

Août 2025

We have ported our Aurora 64B/66B on Efinix Titanium. We have built a nice and convincing demo based on the Efinix Titanium kit. This demo is described in the document below. In principle, this type of document is confidential and accessible only after signing a mutual NDA. Please understand (…)

MachXO5 Example Design

Avril 2025

I2C & Ethernet Reference Design for Lattice MachXO5 Development Boards - Lattice

Discovering Radiant

Janvier 2025

Discover Radiant, the latest FPGA design tool from Lattice ! - Lattice

DSP in Lattice FPGAs (1)

Janvier 2025

Application Note about Inference of Lattice sysDSP block. - Lattice

High-Speed JPEG Video Encoder

Décembre 2024

This is a “dual-core” version of our standard JPEG encoder. It is still compact enough and efficient to fit in a very small low cost FPGA while allowing real time compression at higher resolutions than Full-HD at 60fps. It has an option to generate a video stream optimized for GPU decoding ! (…)

Trainings outside Europe

Juillet 2024

Since most of our Training courses are now delivered Live OnLine, we can reach many parts of the world with an adapted format (typically : shorter daily sessions). Specifically when you have a Team to train, it might make sense to check with us if we can help you efficiently. Don’t worry : if we (…)

Assertions Based Verification

Juillet 2024

If you don’t use Assertions yet, think twice ! You are lagging behind and you miss a huge opportunity to create better code, to enhance your verification, to find bugs faster and to make your life more interesting. Assertion-Based Verification is an old and proven methodology, compulsory in ASIC (…)

Assertions Based Verification

Juillet 2024

If you don’t use Assertions yet, think twice ! You are lagging behind and you miss a huge opportunity to create better code, to enhance your verification, to find bugs faster and to make your life more interesting. Assertion-Based Verification is an old and proven methodology, compulsory in ASIC (…)

Agilex 5 FPGAs

Avril 2024

We currently have three kinds of Agilex 5 boards, shown below. We received one of the very first Intel Kits that are coming out, thanks to our friends at Intel now again Altera France. We have several Arrow AXE5 Eagle boards on which we have ported and tested many of our IPs. Last we got an (…)

History

Avril 2024

In the beginning was Altera ALSE has a long and strong history of three decades successfully using and supporting the Altera FPGA families and tools. And was an Altera Platinum Design partner and Training Center. Not surprisingly, we have developed over nearly 30 years a considerable know-how (…)

La Scala !

Mars 2024

ALSE MILAN IP Carrier Board - Boards

What is IO Checker ?

Mars 2024

If you are involved with designing a board with an FPGA on it, starting with the schematics and ending in a functional PCB, then this article is four you ! Rationale Today more than ever, doing things quickly and right the first time is critical in any project. For HDL and Digital Design, we (…)

Floating Points in FPGAs

Février 2024

Are you tempted about using Floating Point vectors (“Reals”) in your next FPGA project ? Can this be done ? How ? Is it a good idea ? Then this Application Note (an extract from our FPGA Design Training course) is for you… - Application Notes

Floating Points

Février 2024

Are you tempted about using Floating Point vectors (“Reals”) in your next FPGA project ? Can this be done ? How ? Is it a good idea ? Then this Application Note (an extract from our FPGA Design Training course) is for you. - Altera / Intel

UARTs & RS232

Février 2024

In 2024, some may consider that UARTs (and RS232) are a thing of the past. They couldn’t be more wrong ! An RS232 link is the simplest way to exchange any kind of information between to points ! From the simplest microprocessors to the most complex Systems On Chips and Embedded processors, all (…)

The ALSE AVB Milan IP

Janvier 2024

In 2024, ALSE launched an FPGA IP for Milan, thus allowing any company to develop products incorporating the MILAN technology and protocols in record time, with very low effort, and guaranteed performance and compliance. The Milan IP sold and supported by ALSE is (by far) the most complex in the (…)

What is AVB MILAN ?

Janvier 2024

This section and its articles are dedicated to the technology of distributing real-time media contents over Ethernet and more specifically : Audio. We present briefly AVB and MILAN since we are launching in 2024 and AVB-Milan IP. AVB AVB “Audio Video Bridging” is a set of six IEEE standards that (…)

JESD204

Janvier 2024

JESD204 is the Data Converter Serial Interface standard that was created through the JEDEC committee, with the participation of all the industrial providers of high-speed ADC and DACs (including Ti, Analog Devices etc). If you want to use High Speed ADCs or DACs in your project, you need an FPGA (…)

Aurora 64B/66B IP Core on Polarfire

Janvier 2024

We have ported our Aurora 64B/66B on Polarfire, and tested it on the Polarfire kit. This is described in details in the Reference Design Documentation available below. In principle, this type of document is confidential and accessible only after signing a mutual NDA. Please understand that you (…)

Aurora 8B/10B on Polarfire

Janvier 2024

Like we did for our Aurora 64B/66B, we have ported our Aurora 8B/10B on Polarfire, and tested it on the Polarfire kit. This is described in details in the Reference Design Documentation available below. In principle, this type of document is confidential and accessible only after signing a (…)

LiteX and Lattice FPGAs

Janvier 2024

LiteX : Enhancing FPGA development with versatility and integration Author : Florent Kermarrec http://www.enjoy-digital.fr/ Overview of LiteX LiteX is an FPGA framework recognized for its broad compatibility with a range of FPGA platforms, including Lattice, Intel, Xilinx and and new actors (…)

Igloo nano Kit tutorial

Janvier 2024

This is an old Tutorial for a vintage kit ! Surprisingly, you’ll see that the methodology shown here is still valid. This old tutorial show how to use the Igloo nano kit for implementing and testing a UART. It shows how things worked 15 years ago, and you might be surprised to see that things (…)

10G Ethernet on Polarfire

Janvier 2024

End 2023, we have ported several of our IPs on the Microchip Polarfire family, including our 10G Ethernet processor-less IP. In doing so, we have created a Reference Design for the MPF-300 EVAL Kit. The full documentation for this Reference Design is accessible below. - Microchip

ChipBridge (Chip-To-Chip)

Janvier 2024

This IP is ideal to control a lot of peripherals from a centralized high-end (Master) FPGA (or ASIC) ! Connecting and controlling peripherals from the Master directly is typically difficult and inefficient : lack of support for 3.3V I/Os, level translators and ESD protections required, (…)

IPs

Janvier 2024

All our IPs are available on Intel FPGAs. -* AVB MILAN Aurora 64B/66B Aurora 8B/10B Chip-Bridge (chip-to-chip link) 10GEDEK (10G Ethernet processor-less stack) GEDEK (1 Gigabit/100M Ethernet processor-less stack) Remote update (through Ethernet RS232, RS485, SPI …) JESD204B Tx+Rx NAND Flash (…)

High Speed LVDS communication

Mai 2023

Practically all FPGAs, even the low cost ones, offer the capability to create high-speed communication links based on LVDS signalling. If you think it’s complex to use this capability, this article will prove you wrong. LVDS (Low Voltage Differential Signalling) is a standard that uses two (…)

Remote Update for Lattice FPGAs

Avril 2023

ALSE’s IP for remote Update through Ethernet - Lattice

Intel Remote Update Application Note

Janvier 2023

We have updated and re-published this Application Note created in 2010. It explains the principles and implementation of multi-boot in Altera now Intel FPGAs. The actual features available in the Intel FPGAs to allow the use of multiple configuration images in the external memory are actually (…)

Formations en France

Décembre 2022

Attending an ALSE training is 95% guaranteed to be highly productive ! - Fourre-tout / CycloShow

Free IPs

Décembre 2022

For Education purpose, we provide here a number of Free simple IPs (for personal use only !) Even if these blocks are quite simple, the coding style, the functions implemented, and the unitary verification methodology (test benches and behavioral models) are nonetheless very typical and (…)

Design Services

Décembre 2022

No surprise : our core competence is Designing FPGAs (or ASICs), the more complex the better. - Fourre-tout / CycloShow

Ethernet Solutions

Décembre 2022

Did you once evaluate the possibility of connecting an FPGA to Ethernet and transferring data to/from a PC for example ? Did you reach the conclusion that it was very difficult and involved a lot of complex and bulky parts ? Then it’s time to re-consider !!! Our GEDEK IP offers a new paradigm. (…)

Intellectual Properties

Décembre 2022

ALSE Intellectual Property Blocks (“IPs”) are ready-to-use complex FPGA functions that you can buy from A.L.S.E and integrate in your projects. - Fourre-tout / CycloShow

Using the LT24 / ILI9341

Septembre 2022

This (2017) complete Application Note shows how to control the LT24 LCD Display from an FPGA kit. Even if you use a different LCD controller, or a different FPGA kit, you could be interested in the techniques used in this Application Note. - Application Notes

Gowin

Septembre 2022

If you just bought the TEC0117 GOWIN LittleBee FPGA module, you can follow this small Application Note to go through the whole process of setting up the Gowin tools, creating a simple project and testing it on the FPGA board. If you don’t have the board, you can still follow the step to have a (…)

Happy New Year

Janvier 2022

Best Wishes from ALSE The A.L.S.E Team in France wishes you all the best for 2026… … and will be at your side for your Digital Projects with our (FPGA & ASIC) IPs, our Design Services, our Expertise and our Trainings ! - NewsLetter

Aurora 64B/66B IP Core

Novembre 2019

Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers. The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of this protocol, also developed and verified to ensure full (…)

REFLEX CES Stratix 10 boards

Janvier 2018

This page highlights REFLEX CES’ boards based on FPGA Stratix 10, the brand new FPGA by Intel -1- Sargon Instant-Development Kit Stratix 10 FPGA FMC+ PCIe board The Stratix 10 FPGA FMC+ Instant-Development Kit provides developers the best Out-Of-The box experience, combining the Best-In Class (…)

REFLEX CES DevKits

Janvier 2018

REFLEX CES has developed many FPGA Development Kits and FPGA modules. This page highlights some of REFLEX CES’ newest and most powerful kits, based on Arria 10 FPGA. -1- Achilles Instant-Development Kit Arria 10 SoC SoM The Arria 10 SoC SoM provides to developers the best Out-Of-The box (…)

HyperBus / HyperRam Memory Controller

Novembre 2017

The new HyperRAM memories, based on low-power PSRAM technology and using a newly defined HyperBus interface, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications and are an excellent fit for many projects. They (…)

Aurora 8b/10b IP Core

Octobre 2017

The Aurora 8b/10b IP Core is a lightweight high-speed serial protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers. For Xilinx users, Aurora is available as a Xilinx Logicore IP. Our IP makes Aurora available to ASICs and to other FPGAs, (…)

Designing for Stratix 10 FPGAs

Août 2017, par Bertrand Cuzeau

The new Intel 14 nm Stratix 10 FPGA family offer unprecedented performance. However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. This (…)

Designing for Stratix 10 FPGAs

Août 2017

The new Intel 14 nm Stratix 10 FPGA family offer unprecedented performance. However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. This (…)

NUMERIC_STD Issue.

Mars 2017, par Bertrand Cuzeau

This article describes an error that I found only recently in NUMERIC_STD. Conclusion : do not multiply signed or unsigned vectors by an integer ! - VHDL helper

NUMERIC_STD Issues.

Mars 2017

This article describes two problems I found in NUMERIC_STD. Conclusions : do not multiply signed or unsigned vectors by an integer, and be careful with with the resize function ! - VHDL helper

VHDL Coding Guide

Novembre 2016, par Bertrand Cuzeau

This VHDL Coding Guide can significantly help improve your coding style as well as the quality of your designs ! - VHDL Coding Guide

VHDL Coding Guide

Novembre 2016

This VHDL Coding Guide can significantly help improve your coding style as well as the quality of your designs ! - VHDL Coding Guide

PowerLink

Novembre 2016, par Bertrand Cuzeau, Sylvain Lesne

POWERLINK is our choice as of Standard Real-time Industrial Ethernet Network. We have acquired a serious know-how and we have the capability to quickly port this network to any FPGA, as we have done for the Altera Max10 when it became available. - Industrial (…)

PowerLink

Novembre 2016

POWERLINK is our choice as of Standard Real-time Industrial Ethernet Network. We have acquired a serious know-how and we have the capability to quickly port this network to any FPGA, as we have done for the Altera Max10 when it became available. - Industrial (…)

Synchronous SRAM (SSRAM) Controller

Novembre 2016, par Etienne Laurendeau

Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low (…)

Synchronous SRAM (SSRAM) Controller

Novembre 2016

Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low (…)

Ultra Low Latency Network

Octobre 2016, par Bertrand Cuzeau

No existing Industrial Network provided the performance (latency & throughput) that a customer application required, so we have developed this Ultra-Low Latency redundant network. - Industrial Ethernet

Ultra Low Latency Network

Octobre 2016, par Bertrand Cuzeau

No existing Industrial Network provided the performance (latency & throughput) that a customer application required, so we have developed this Ultra-Low Latency redundant network. - Industrial Ethernet

PCI Express

Octobre 2016, par Bertrand Cuzeau, Guillaume JOLI

Most FPGA designers still find it very difficult to use PCI Express in a project. We have designed a lot of PCI Express IPs and we do not believe in the “off-the-shelf” model. We can create just the IP you need, even including the proper driver, in a matter of days. - (…)

PCI Express for FPGAs

Octobre 2016, par Bertrand Cuzeau, Guillaume JOLI

Most FPGA designers still find it very difficult to use PCI Express in a project. We have designed a lot of PCI Express IPs and we do not believe in the “off-the-shelf” model. We can create just the IP you need, even including the proper driver, in a matter of days. - (…)

Embedded Software

Septembre 2016, par Sylvain Lesne

With more and more complex and powerful Processor cores included in recent FPGAs, we have developed a deep competence in Embedded Systems and Embedded Software. It covers from embedded soft cores to ARM High Performance Systems. And indeed, beyond bare metal, we are clearly focused on Embedded (…)

Embedded Software

Septembre 2016, par Sylvain Lesne

With more and more complex and powerful Processor cores included in recent FPGAs, we have developed a deep competence in Embedded Systems and Embedded Software. It covers from embedded soft cores to ARM High Performance Systems. And indeed, beyond bare metal, we are clearly focused on Embedded (…)

Quad SPI Controller

Septembre 2016, par Etienne Laurendeau

For an FPGA-based project, replacing bulky, pin-consuming, and complex Parallel Flash Memories by modern Quad-SPI Flash devices is very exciting in many respects. It drastically reduces the FPGA pin count and thus enables smaller (and cheaper) packages. It also reduces the power consumption, (…)

Quad SPI Controller

Septembre 2016, par Etienne Laurendeau

For an FPGA-based project, replacing bulky, pin-consuming, and complex Parallel Flash Memories by modern Quad-SPI Flash devices is very exciting in many respects. It drastically reduces the FPGA pin count and thus enables smaller (and cheaper) packages. It also reduces the power consumption, (…)

NAND Flash Controller

Septembre 2016, par Etienne Laurendeau

NAND Flash memories are attractive due to their very high density and low price. However, when compared to NOR Flash Memories, they are challenging because they are not fault-free (they need ECC Correction, Bad Block management, etc …) and they are organized like disk drives, with atomic (…)

NAND Flash Controller

Septembre 2016, par Etienne Laurendeau

NAND Flash memories are attractive due to their very high density and low price. However, when compared to NOR Flash Memories, they are challenging because they are not fault-free (they need ECC Correction, Bad Block management, etc …) and they are organized like disk drives, with atomic (…)

PSRAM Controller

Septembre 2016, par Etienne Laurendeau

Power consumption is more and more critical in many applications, such as battery-powered equipments, very low power applications and other fields like automotive, military, etc … Thus, choosing and using a very low power external memory such as a PSRAM (Pseudo-Static RAM) memory can be a very (…)

SRAM Controller

Septembre 2016, par Etienne Laurendeau

A.L.S.E has developed a very compact and efficient Static RAM controller that can be easily integrated in any FPGA project. Main Technical Features High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead. (…)

Do I need SystemVerilog ?

Septembre 2016, par Bertrand Cuzeau

We assume you are an FPGA Designer. If you’re not already fluent in SystemVerilog (SV), then you may wonder whether it’s worth the effort (to learn this huge new language). We’ll try here to provide some answers. You’ve been using VHDL for years (or just beginning), and you hear sometimes that (…)

IndEEx

Septembre 2016, par Bertrand Cuzeau

IndEEx stands for INDustrial Ethernet EXtension. We developed this little inexpensive board in just a few days for the urgent need to add two Industrial Ethernet PHYs to a DE2-115 kit (which includes already two Gigabit PHYs). This extension is compatible with many inexpensive FPGA kits like (…)

Nina

Septembre 2016, par Bertrand Cuzeau

Nina is a very simple add-on board that can be plugged into many cheap FPGA kits including the BeMicroMax10, the DE0-nano, the DE2 series etc. It provides a lot of extra peripherals and features including Ethernet and many more. Extend low-cost kits with Ethernet and many extra features ! Nina (…)

Utilities

Septembre 2016, par Bertrand Cuzeau

© 2009 ALSE. All rights reserved. NOTICE OF DISCLAIMER about Free IPs and other information on the ALSE Web site. ALSE is providing design, code, or information “as is.” By providing the design, code, or information ALSE makes no representation that this implementation is free from any claims of (…)

VHDL Examples

Septembre 2016, par Bertrand Cuzeau

If you are looking for well-written code to analyze, or coding examples, please check also our Free IP section where you can find the source code of many IPs, which are reasonably simple to understand while implementing all the concepts needed for designing complex functions. We have dedicated (…)