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REFLEX CES DevKits

Janvier 2018

REFLEX CES has developed many FPGA Development Kits and FPGA modules. This page highlights some of REFLEX CES’ newest and most powerful kits, based on Arria 10 FPGA. -1- Achilles Instant-Development Kit Arria 10 SoC SoM The Arria 10 SoC SoM provides to developers the best Out-Of-The box (…)

HyperBus / HyperRam Memory Controller

Novembre 2017

The new HyperRAM memories, based on low-power PSRAM technology and using a newly defined HyperBus interface, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications and are an excellent fit for many projects. They (…)

Aurora 8b/10b IP Core

Octobre 2017

The Aurora 8b/10b IP Core is a lightweight high-speed serial protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers. For Xilinx users, Aurora is available as a Xilinx Logicore IP. Our IP makes Aurora available to ASICs and to other FPGAs, (…)

Designing for Stratix 10 FPGAs

Août 2017, par Bertrand Cuzeau

The new Intel 14 nm Stratix 10 FPGA family offer unprecedented performance. However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. This (…)

Designing for Stratix 10 FPGAs

Août 2017

The new Intel 14 nm Stratix 10 FPGA family offer unprecedented performance. However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. This (…)

NUMERIC_STD Issue.

Mars 2017, par Bertrand Cuzeau

This article describes an error that I found only recently in NUMERIC_STD. Conclusion : do not multiply signed or unsigned vectors by an integer ! - VHDL helper

NUMERIC_STD Issues.

Mars 2017

This article describes two problems I found in NUMERIC_STD. Conclusions : do not multiply signed or unsigned vectors by an integer, and be careful with with the resize function ! - VHDL helper

VHDL Coding Guide

Novembre 2016, par Bertrand Cuzeau

This VHDL Coding Guide can significantly help improve your coding style as well as the quality of your designs ! - VHDL Coding Guide

VHDL Coding Guide

Novembre 2016

This VHDL Coding Guide can significantly help improve your coding style as well as the quality of your designs ! - VHDL Coding Guide

PowerLink

Novembre 2016, par Bertrand Cuzeau, Sylvain Lesne

POWERLINK is our choice as of Standard Real-time Industrial Ethernet Network. We have acquired a serious know-how and we have the capability to quickly port this network to any FPGA, as we have done for the Altera Max10 when it became available. - Industrial (…)